The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
On behalf of the ISQED 2013 conference and technical committees, we are pleased to welcome you to the 14th International Symposium on Quality Electronic Design, ISQED 2013. This conference is the premier multidisciplinary design and design automation conference, aimed at bridging the gap between and integration of, electronic design tools and processes, integrated circuit technologies, processes,...
Timing the transition of a processor design to a new technology poses a provocative tradeoff. On the one hand, transitioning as early as possible offers a significant competitive advantage, by bringing improved designs to market early. On the other hand, an aggressive strategy may prove to be unprofitable, due to the low manufacturing yield of a technology that has not had time to mature. We propose...
Microchannel liquid cooling shows great potential in cooling 3D processors. However, the cooling of 3D processors is limited due to design-time and run-time challenges. Moreover, in new technologies, the processor power density is continually increasing and this will bring more serious challenges to liquid cooling. In this paper, we propose two thermal control techniques: 1) Core Vertically Placed...
3D integrated circuits (3DICs) with through-silicon vias (TSVs) are an important direction for semiconductor-based products and “More than Moore” scaling. However, 3DICs bring simultaneous challenges of reliability (power and temperature in stacks of thinned die) as well as variability (performance and power) in advanced technology nodes. In this paper, we study variability-reliability interactions...
Three dimensional (3D) integrated circuit (IC) technology is emerging as a potential alternative to address the physical limitations in miniaturization of the current 2D semiconductor devices. The 3D IC integration is based on the concept of through-silicon vias (TSV) and vertical stacking of multiple active layers. TSV-based 3D IC's offer significant advantages in performance due to reduction in...
A 2.5D/3D multi die interposer with TSV (Through Silicon Via) allows massive wide parallel busses between memory and logics devices, improves speed, and significantly reduces power consumption. The TSV and silicon interposer are amongst the most promising technologies that offer the greatest vertical interconnects density. This new establishment will change the semiconductor industry paradigm for...
A compact NBTI model is presented by directly solving the reaction-diffusion (RD) equations in a simple way. The new model can handle arbitrary stress conditions without solving time-consuming equations and is hence very suitable for analog/mixed-signal NBTI simulations in SPICE-like environments. The model has been implemented in Cadence ADE with Verilog-A and also takes the stochastic effect of...
Ternary content addressable memory (TCAM), which can store 0, 1 and X in its cells, is widely used to store routing tables in network routers. Meanwhile, NBTI (Negative Bias Temperature Instability) and PBTI (Positive Biased Temperature Instability), which increase Vth and degrade transistor switching speed, have become major reliability challenges. In this paper, we propose a novel TCAM architecture...
Negative bias temperature instability (NBTI) has become a serious concern for the lifetime reliability of integrated circuits. On-line aging prediction is a promising way to prevent NBTI-induced circuit failure. However, the ever-increasing parameter variations, design complexity and area overhead degrade the effectiveness of such delay detection-based scheme. In this paper, we propose to use the...
Transistor aging due to Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) is one of the major reliability issues of VLSI circuits fabricated at nanometer technology nodes. Transistor aging increases the circuit delay over the time and ultimately leads to lifetime reduction of VLSI chips. Accurate aging-aware timing analysis is a key requirement to consider these effects in the design...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.